/*=============================================================================
# FileName    : spi_slave_core.v
# Author      : author
# Email       : email@email.com
# Description : slave中的send模块主要用于和其他设备的maste通信
                例如,slave收到常用的addr+cmd+read_data
# Version     : 1.0
# LastChange  : 2018-04-10 22:25:43
# ChangeLog   : 
=============================================================================*/
`timescale  1 ns/1 ps

module spi_slave_core #
(
    parameter               DATA_W = 8
)
(
    input   wire                clk,
    input   wire                rst,

    /*
     * 需要响应给spi_master 读的数据 
     */
    input   wire                m_axi_tready,
    output  wire                m_axi_tvalid,
    output  wire [DATA_W-1:00]  m_axi_tdata,

    /*
     * 输出从spi master接收到的数据
     */
    output  wire                s_axi_tready,
    input   wire                s_axi_tvalid,
    input   wire [DATA_W-1:00]  s_axi_tdata,
    /*port*/

    input   wire [07:00]        config_reg,

    input   wire                sclk,
    input   wire                scs,
    input   wire                mosi,
    output  wire                miso
);

spi_slave_send_core     #
(
        .DATA_W         (       8               )
)
spi_slave_send_coreEx01
(
    .clk            (       clk             ),
    .rst            (       rst             ),
    .config_reg     (       config_reg      ),
    .sclk           (       sclk            ),
    .scs            (       scs             ),
    .miso           (       miso            ),
    .s_axi_tready   (       s_axi_tready    ),
    .s_axi_tvalid   (       s_axi_tvalid    ),
    .s_axi_tdata    (       s_axi_tdata     )
) ;

spi_slave_recv_core     #
(
        .DATA_W(       8               )
)
spi_slave_recv_coreEx01
(
    .clk            (       clk             ),
    .rst            (       rst             ),
    .config_reg     (       config_reg      ),
    .sclk           (       sclk            ),
    .scs            (       scs             ),
    .mosi           (       mosi            ),
    .m_axi_tready   (       m_axi_tready    ),
    .m_axi_tvalid   (       m_axi_tvalid    ),
    .m_axi_tdata    (       m_axi_tdata     )
) ;
endmodule
